In recent years, a new nonvolatile semiconductor storage device which stores information of one bit therein by changing a resistance of the memory has been actively researched and developed. The PRAM (Phase change RAM) using a phase change resistance element made of chalcogenide alloy or the like as a memory element is an example of such nonvolatile semiconductor storage device. PRAM utilizes a property that a resistance value of the phase change resistance element changes depending on a heating method (or a cooling method after heating). Most typically, the phase change resistance element is heated by passing a current through the phase change resistance element to generate Joule heat. Another example is the ReRAM (Resistive RAM) using a metal oxide resistance element made of perovskite oxide or the like as the memory element. ReRAM utilizes a property that a resistance value of the metal oxide resistance element made of perovskite oxide or the like changed depending on a voltage or a current applied to the metal oxide resistance element. A solid electrolyte memory using solid electrolyte resistance element made of solid electrolyte such as copper sulfide as the memory element has been researched and developed. The solid electrolyte resistance element is an element utilizing transfer of atoms in the solid electrolyte and a resistance value of the solid electrolyte resistance element changes depending on a polarity of the applied voltage. The solid electrolyte memory utilizes such property of the solid electrolyte resistance element.
Read operations of data stored in these memory elements are commonly performed by detecting the resistance value. One of typical methods of detecting the resistance value is a method of providing a reference cell in which prescribed data is previously programmed in a memory cell and comparing a signal (typically current signal) obtained from the memory cell in a selected state with a signal obtained from the reference cell. For example, the reference cell in which data “0” is programmed and the reference cell in which data “1” is programmed are prepared and an average current value of currents passing through these reference cells is compared to a current value of a current passing through the memory cell to perform the read operation.
Like other many memory devices, the above-mentioned the PRAM, the ReRAM and the solid electrolyte memory inevitably encounter data error in the memory cell. In the case of the PRAM, since data is written based on variation in the heating methods, the PRAM is susceptible to an operating environment, in particular, an environmental temperature. For example, when the PRAM optimized at room temperature is operated in an environment of about 100° C., the memory cell which normally operates at room temperature can defectively operate. Furthermore, since a write operation and the read operation use a same current path, the stored data can be rewritten by the read operation. On the other hand, in the case of the ReRAM and the solid electrolyte memory, control of the write operation is complicated, for example, the write operation needs to be changed depending on data to be written, and the write operation may not be normally performed due to power voltage variation. Like the PRAM, since the write operation and the read operation use the same current path, the stored data can be rewritten by the read operation. As described above, in the PRAM, the ReRAM and the solid electrolyte memory, it is hard to prevent a soft error caused by using the same current path in the write operation and the read operation, resulting in that undesired inversion of the stored data inevitably occurs at a low probability.
To address such data error, as in the other many memory devices, it is desired that the soft error is relieved according to an ECC (Error check and correction) technique using an error correction code. However, in the case of the soft error caused by rewriting of the stored data in the read operation, thought should be given to a fact that it is unclear whether the data cell or the reference cell should be corrected. The reference cell is accessed in the read operation at all times and may be undesirably inverted at a low probability. Accordingly, even if the data error is detected, when the data stored in the data cell is merely corrected, the soft error possibly cannot be relieved in the end.
In addition, in an error correction in the PRAM, the ReRAM and the solid electrolyte memory, desirably, at an error detection, it can be predicted or decided which of the data cell or the reference cell has the soft error at a high probability. Furthermore, it is desired that even when the data error exists in the reference cells, the error correction can be performed. The data error in the reference cell tends to appear as a burst error. However, when the burst error due to the data error in the reference cell affects a too wide range, the error correction cannot be performed.
From one aspect of the error correcting method, it can be considered that both the data cell with error and the reference cell used for reading of the data cell are unconditionally corrected at the error detection. However, simultaneously performing the write operation in the data cell and the reference cell leads to complication of an address decoder and requires a dedicated writing circuit for the reference cell. Generally, a voltage or a current necessary for the write operation of the PRAM, the ReRAM and the solid electrolyte memory is not small and an area of the writing circuit is large. In addition, the write operation in the memory cell which does not require an error correction is performed, which is inefficient. Therefore, such error correcting method leads to an increase in the circuit area and power consumption.
Against this backdrop, there is demand for a technique capable of performing the error correction without overhead of the circuit area and power consumption even if the data error occurs in any of the data cell and the reference cell.